Homework 1:
From chapter 1 in the handouts, problems 2, 9, 10,
11, 12, 13, 14.
Solution.ps, .pdf
Homework 2:
From chapter 2 in the handouts, problems 2, 5, 6,
7, 8, 11.
Solution.ps, .pdf
Homework 3:
- Design and compare the total gate delay for
the following adders (n=32, r=3)
- a) Conditional Sum Adder
- b) Single-level carry skip adder (fixed block size =r-1)
- c) CLA
- From chapter 3 in the handouts, problems 2, 3 (assume
r=3), and 5.
- For extra credit: Read this paper (.ps, .pdf) and
design a fast multiple level carry skip adder with variable block size.
(n=48, r=5)
Solution.ps, .pdf
Homework 4:
From chapter 4 in the handouts, problems
1,4,8,11,13.
Solution.ps, .pdf
Homework 5:
- Determine the Booth encoding table for X*(Yh-Yl)
where Yh = yyyy0000 and Yl = 0000yyyy and y denotes a
bit that can be either 0 or 1, i.e. Yh is the high part and Yl
is the low part.
- From chapter 5 in the handouts, problems 3, 5, 7.
Solution.ps, .pdf