Andy Bartolo

Gates 422
353 Jane Stanford Way
Stanford, CA 94305-5008

Iastname where stanford point edu [PGP]

I'm a sixth-year Ph.D. student in computer science. I am primarily interested in software & hardware support for high-performance computing immersed in memory. I work on the N3XT project in Stanford's Robust Systems Group, advised by Prof. Subhasish Mitra.

Here are some articles on our work.

Publications

MC-ELMM: Multi-Chip Endurance-Limited Memory Management
A. M. Bartolo, M. M. Sabry Aly, G. Michelogiannakis, S. Mitra
2023 [ACM MEMSYS]

Illusion of large on-chip memory by networked computing chips for neural network inference
R. M. Radway, A. M. Bartolo, P. C. Jolly, Z. F. Khan, B. Q. Le, P. Tandon, T. F. Wu, Y. Xin, E. Vianello, P. Vivet, E. Nowak, H.-S. P. Wong, M. M. Sabry Aly, E. Beigne, M. Wootters, S. Mitra
2021 [Nature Electronics]

Heterogeneous 3D nano-systems: The N3XT approach?
D. Rich, A. M. Bartolo, C. Gilardi, B. Q. Le, H. Li, R. Park, R. M. Radway, M. M. Sabry Aly, H.-S. P. Wong, S. Mitra
2020 [Springer NANO-CHIPS 2030]

A 43pJ/Cycle Non-Volatile Microcontroller with 4.7µs Shutdown/Wake-up
T. F. Wu, B. Q. Le, R. Radway, A. M. Bartolo, W. Hwang, S. Jeong, H. Li, P. Tandon, E. Vianello, P. Vivet, E. Nowak, M. K. Wootters, H.-S. P. Wong, M. M. Sabry Aly, E. Beigne, S. Mitra
2019 [IEEE ISSCC]

The N3XT Approach to Energy-Efficient Abundant-Data Computing
M. M. Sabry Aly, T. F. Wu, A. M. Bartolo, Y. H. Malviya, W. Hwang, G. Hills, I. Markov, M. Wootters, M. M. Shulaker, H.-S. P. Wong, S. Mitra
2018 [Proc. IEEE]

Teaching

CS 157, Fall 2016-2017 (TA)
EE 108, Fall 2015-2016 (TA)

Industry

Samsung Semiconductor, summer 2018

Selected Projects

Open Source

My GitHub contains code from past and ongoing class, research, and personal projects. In particular:

ClusterSim is a massively-parallel architectural simulator. It both utilizes the resources of an entire HPC cluster, and supports simulation of whole-cluster applications. ClusterSim is part of a larger effort to investigate the benefits of N3XT for large-scale multi-chip workloads.

ENDUReR is an endurance mitigation mechanism for emerging nonvolatile memory families, such as resistive RAM (RRAM). It includes a coherent write buffer and periodic remapping algorithm.