Yatish Turakhia

I am a third year PhD candidate at the Electrical Engineering Department of Stanford University. I am highly fortunate to be co-advised by Professor Bill Dally and Professor Gill Bejerano. My current research focuses designing a co-processor for accelerating a wide-range of algorithms involving genomic sequence alignment – from read assembly to remote homology search. In my first year at Stanford, I also worked on a project to reduce the wire energy of L1-cache in mobile workloads (link). I am a recipient of the NVIDIA Graduate Fellowship (2016).

Prior to Stanford, I did my B.Tech and M.Tech (Microelectronics) in Electrical Engineering, along with a Minor in Computer Science and Engineering, from Indian Institute of Technology, Bombay (IIT-B). There, I spent wonderful years working at the High Performance Computing (HPC) lab, headed by Professor Sachin Patkar. My undergraduate research was also supervised by Professor Diana Marculescu and Professor Siddharth Garg, particularly during my two summer internships at Carnegie Mellon University.


Research Interests:
Computer Architecture, Computational Genomics.

Publications:
[1] B. Raghunathan, Y. Turakhia, S. Garg, D. Marculescu, “Cherry-Picking: Exploiting Process Variations in Dark-Silicon Homogeneous Chip Multi-Processors,” in Proc. IEEE/ACM Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March 2013 (Paper).

[2] Y. Turakhia, B. Raghunathan, S. Garg, D. Marculescu, “HaDeS: Architectural Synthesis for Heterogeneous Dark Silicon Chip Multi-processors,” in Proc. ACM/IEEE Design Automation Conference (DAC), Austin, TX, June 2013 (Paper).

[3] V. Kumar, P. Engineer, M. Datar, Y. Turakhia, S. Agarwal, S. Diwale and S. Patkar, “Framework for Application Mapping over Packet-switched Network of FPGAs : Case studies,” FPGAs for Software Programmers (FSP),  London, UK, September 2015 (Paper).

[4] Y. Turakhia, G. Liu, S. Garg, D. Marculescu, “Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-threaded Applications”,  IEEE Transactions on Computers (TC), 2016 (Paper).

Experience:
  • Summer 2016 - Qualcomm Research (San Diego, CA)
    Research Intern in SoC Architecture Research (SAR) group.
  • Summer 2015 - Apple Inc. (Cupertino, CA)
    Research Intern in Platform Architecture.
  • Summer 2013 - Carnegie  Mellon University (Pittsburgh, PA)
    ECE Research Intern (advised by Prof. Diana Marculescu and Prof. Siddharth Garg).
  • Summer 2012 - Carnegie  Mellon University (Pittsburgh, PA)
    ECE Research Intern (advised by Prof. Diana Marculescu and Prof. Siddharth Garg).

Teaching:
Stanford University

   Teaching Assistant - EE382C: Interconnection Networks (Spring 2016)
.
IIT Bombay
 
Teaching Assistant - EE224: Digital Systems (Spring 2014).
 
Teaching Assistant - EE717: Advanced Computing for Electrical Engineers (Fall 2013).

Contact:
Office:
Gates Room 214, 353 Serra Mall, Stanford, CA, 94305, U.S.
Email:  yatisht [at] stanford [dot] edu