Xuan Yang is a Ph.D. student in the Department of Electrical Engineering, Stanford University. Currently she is working with Professor Mark Horowitz in Stanford VLSI Research Group. Her research interests lie in the area of computer architecture and systems, focusing on energy-efficient and high-performance acceleration for deep learning, computer vision based applications. Specifically, She designed an systematic framework to analyze the design space of Deep Neural Network (DNN) accelerators, including the design choices of dataflow, loop transformation and resource allocation. Besides, she developed an automatic hardware generation toolchain that can generate DNN accelerators from a Domain-Specific Language (DSL) called Halide.
She also received a Master of Science degree at Stanford in 2014. Before coming to Stanford, She got Bachelor of Engineering degree in Mechatronic Engineering in Beijing Institute of Technology, Beijing, China, in July, 2012.
|Sep. 2012 to Present||Ph.D.||Stanford University||Stanford, CA, U.S.|
|Sep. 2012 to Jun. 2014||M.S.||Stanford University||Stanford, CA, U.S.|
|Aug. 2008 to Jul. 2012||B.E.||Beijing Institute of Technology||Beijing, China|
|Jun. 2018 to Sep. 2018||Google AI Perceptron||Mountain View, CA, U.S.|
|Jun. 2016 to Sep. 2016||Apple||Cupertino, CA, U.S.|
|Jun. 2014 to Sep. 2014||Samsung Research America||San Jose, CA, U.S.|
|Fall 2013||Teaching Assistant||EE 271 Introduction to VLSI Systems|
Office: Gates Hall Room 356
Address: 353 Serra Mall, Stanford, CA, 94305, U.S.
Email: xuany [at] stanford [dot] edu