Journal Publications:

  1. C. Gilardi, R. Bennett, Y. Yoon, E. Pop, H.-S.P. Wong and S. Mitra , “Extended Scale Length Theory for Low-Dimensional Field-Effect Transistors,” IEEE Trans. Electron Devices, 2022.
  2. L. Yang, R.M. Radway, Y.-H. Chen, T.F. Wu, H. Liu, E. Ansari, V. Chandra, S. Mitra and E. Beigne, “3D Stacked Neural Network Accelerator Architectures for AR/VR Applications,” IEEE Micro, 2022.
  3. M. Fadiheh, A. Wezel, J. Müller, J. Bormann, S. Ray, J. Fung, S. Mitra, D. Stoffel and W. Kunz, “An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors,” IEEE Trans. Computers, 2022.
  4. K. Prabhu, M. Giordano, K. Koul, R. Radway, A. Gural, R. Doshi, Z. Khan, J. Kustin, T. Liu, G. Lopes, V. Turbiner, W-S. Khwa, Y-D. Chih, M-F. Chang, G. Lallement, B. Murmann, S. Mitra and P. Raina, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” IEEE Journal Solid-State Circuits, Special Issue on Symp. VLSI Circuits, 2022.
  5. Q. Lin, G. Pitner, C. Gilardi, S.-K. Su, Z. Zhang, E. Chen, P. Bandaru, A. Kummel, M. Passlack, H. Wang, S. Mitra and H.-S. P. Wong, “Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs,” IEEE Electron Device Letters, 2022.
  6. R. Vikhu, S. Madugula, L. Grosberg, A. Gogliettino, P. Hottowy, W. Dabrowski, A. Sher, A. Litke, S. Mitra and E. J. Chichilnisky, “Spatially Patterned Bi-electrode Epiretinal Stimulation for Axon Avoidance at Cellular Resolution,” Journal of Neural Engineering, 2021.
  7. P. Tandon, N. Bhaskhar, N. Shah, S. Madugula, L. Grosberg, V. Fan, P. Hottowy, W. Dabrowski, A. Sher, A. Litke, E. J. Chichilnisky and S. Mitra, “Automatic Identification of Axon Bundle Activation for Epiretinal Prosthesis,” IEEE Trans. Neural Systems and Rehabilitation Engineering, 2021.
  8. R. Radway, A. Bartolo, P. Jolly, Z. Khan, B. Le, P. Tandon, T. Wu, Y. Xin, E. Vianello, P. Vivet, E. Nowak, H.-S.P. Wong, M.M. Sabry, E. Beigne, M. Wootters and S. Mitra, “Illusion of Large On-Chip Memory by Networked Computing Chips for Neural Network Inference,” Nature Electronics, 2021.
  9. E R. Hsieh, X. Zheng, B.Q. Le, Y. C. Shih, R.M. Radway, M. Nelson, S. Mitra and S. Wong, “Four-Bits-per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array,” IEEE Electron Device Letters, 2021.
  10. B. Le, A. Levy, T. Wu, R. Radway, E. Hsieh, X. Zheng, M. Nelson, P. Raina, H.-S.P. Wong, S.S. Wong and S. Mitra, “RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-per-Cell RRAM Arrays,” IEEE Trans. Electron Devices, 2021.
  11. H.-S.P. Wong, K. Akarvardar, D. Antoniadis, J. Bokor, C. Hu, T.-J. King-Liu, S. Mitra, J. Plummer and S. Salahuddin, “A Density Metric for Semiconductor Technology,” Proceedings of the IEEE, 2020.
  12. J.-P. Noel, M. Pezzin, R. Gauchi, J.-F. Christmann, M. Kooli, H.-P. Charles, L. Ciampolini, M. Diallo, F. Lepin, B. Blampey, P. Vivet, S. Mitra and B. Giraud, “A 35.6TOPS/W/mm² 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications,” IEEE Solid-State Circuits Letters, 2020.
  13. S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, L. Pileggi and S. Mitra, “Split-Chip Design to prevent IP Reverse Engineering,” IEEE Design and Test, 2020.
  14. R. Park, H. Kim, G. Pitner, C. Neumann, S. Mitra and H.-S.P. Wong, “Molybdenum oxide on carbon nanotube: Doping stability and correlation with work function,” Journal Applied Physics, 2020.
  15. D. Muratore, P. Tandon, M. Wootters, E.J. Chichilnisky, S. Mitra and B. Murmann, “A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording,” IEEE Trans. Biomedical Circuits and Systems, Special Issue on IEEE Intl. Symp. Circuits and Systems, 2019 (Invited).
  16. M. Bishop, H.-S.P. Wong, S. Mitra and M. Shulaker, “Monolithic Three-Dimensional Integration,” IEEE Micro, Special Issue on Monolithic 3D Integration, 2019 (Invited).
  17. M. Aly, T.F. Wu, A. Bartolo, Y. Malviya, W. Hwang, G. Hills, I. Markov, M. Wootters, M. Shulaker, H.-S.P. Wong and S. Mitra, “The N3XT Approach to Energy-Efficient Abundant-Data Computing,” Proceedings of the IEEE, Special Issue on Nonsilicon, Non-von Neumann Computing – Part I, Jan. 2019 (Invited, Cover Feature).
  18. B. Le, A. Grossi, E. Vianello, T. Wu, G. Lama, E. Beigne, H.-S.P. Wong and S. Mitra, “Resistive RAM with Multiple Bits per Cell: Array-Level Demonstration of 3 Bits per Cell,” IEEE Trans. Electron Devices, Feb. 2019 (Special Research Highlight by Nature Electronics).
  19. A. Grossi, E. Vianello, M. Aly, M. Barlas, L. Grenouillet, J. Coignus, E. Beigne, T. Wu, B. Le, M. Wootters, C. Zambelli, E. Nowak and S. Mitra, “Resistive RAM Endurance: Array-level Characterization and Correction Techniques Targeting Deep Learning Applications,” IEEE Trans. Electron Devices, 2019.
  20. G. Pitner, G. Hills, J. Llinas, K.-M. Persson, R. Park, J. Bokor, S. Mitra and H.-S.P. Wong, “Low-Temperature Side-Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length,” Nanoletters, 2019.
  21. G. Hills, M. Garcia Bardon, G. Doornbos, D. Yakimets, P. Schuddinck, R. Baert, D. Jang, L. Matti, Y. Sherazi, D. Rodopoulos, R. Ritzenthaler, C.-S. Lee, A. Thean, I. Radu, A. Spessot, P. Debacker, F. Catthoor, P. Raghavan, M. Shulaker, H.-S.P. Wong and S. Mitra, “Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI,” IEEE Trans. Nanotechnology, 2018.
  22. T. Wu, H. Li, P.-C. Huang, A. Rahimi, G. Hills, B. Hodson, W. Hwang, J. Rabaey, H.-S.P. Wong, M. Shulaker and S. Mitra, “Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and their Monolithic 3D Integration,” IEEE Journal Solid-State Circuits, Special Issue on IEEE Intl. Solid-State Circuits Conf., Nov. 2018 (Invited).
  23. E. Cheng, S. Mirkhani, L. Szafaryn, C.-Y. Cher, H. Cho, K. Skadron, M. Stan, K. Lilja, J. Abraham, P. Bose and S. Mitra, “Tolerating Soft Errors in Processor Cores using CLEAR (Cross-Layer Exploration for Architecting Resilience),” IEEE Trans. CAD, 2018.
  24. E. Singh, D. Lin, C. Barrett and S. Mitra, “Logic Bug Detection and Localization using Symbolic Quick Error Detection,” IEEE Trans. CAD, 2018.
  25. K. Campbell, D. Lin, L. He, L. Yang, S. Gurumani, K. Rupnow, S. Mitra and D. Chen, “Hybrid Quick Error Detection: Validation and Debug of SoCs through High-Level Synthesis,” IEEE Trans. CAD, 2018.
  26. M. Shulaker, G. Hills, R. Park, R.T. Howe, K. Saraswat, H.-S.P. Wong and S. Mitra, “Three-dimensional Integration of Nanotechnologies for Computing and Data Storage on a Single Chip,” Nature, 2017 (Special News and Views feature by Nature).
  27. L. Grosberg, K. Ganesan, G. Goetz, S. Madugula, N. Bhaskhar, V. Fan, P. Li, P. Hottowy, W. Dabrowski, A. Sher, A. Litke, S. Mitra and E.J. Chichilnisky, “Activation of Ganglion Cells and Axon Bundles using Epiretinal Electrical Stimulation,” Journal of Neurophysiology, 2017 (Selected for APSselect, a collection from the APS that showcases some of the best recently published articles in physiological research).
  28. H. Li, T. Wu, S. Mitra and H.-S.P. Wong, “Resistive RAM-Centric Computing: Design and Modeling Methodology,” IEEE Trans. Circuits and Systems I, 2017.
  29. R. Park, G. Hills, J. Sohn, S. Mitra, M. Shulaker and H.-S.P. Wong, “Hysteresis-free Carbon Nanotube Field-Effect Transistors,” ACS Nano, 2017.
  30. H. Cho, C.-Y. Cher, T. Shepherd, E. Cheng and S. Mitra, “System-level Effects of Soft Errors in Uncore Components,” IEEE Trans. CAD, 2017.
  31. E. Singh, D. Lin, C. Barrett and S. Mitra, “Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions,” IEEE Design and Test, Special Issue on Top Papers from ITC 2015, Nov.-Dec. 2016 (Invited).
  32. M. Shulaker, H.-S.P. Wong and S. Mitra, “Computing with Carbon Nanotubes,” IEEE Spectrum, July 2016 (Invited).
  33. T. Wu, K. Ganesan, A. Hu, H.-S.P. Wong, S. Wong and S. Mitra, “TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits,” IEEE Trans. CAD, 2016.
  34. R. Park, M. Shulaker, G. Hills, L. Liyanage, S. Lee, A. Tang, S. Mitra and H.-S.P. Wong, “Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution,” ACS Nano, March 2016.
  35. G. Gielen, J. Van Rethy, J, Marin, M. Shulaker, G. Hills, H.-S.P. Wong and S. Mitra, “Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies,” IEEE Trans. Circuits and Systems I, 2016.
  36. M. Aly, M. Gao, G. Hills, C-S Lee, G. Pitner, M. Shulaker, T. Wu, M. Asheghi, J. Bokor, F. Franchetti, K. Goodson, C. Kozyrakis, I. Markov, K. Olukotun, L. Pileggi, E. Pop, J. Rabaey, C. Ré, H.-S.P. Wong and S. Mitra, “Energy-Efficient Abundant-Data Computing: The N3XT 1,000X,” IEEE Computer, Special Issue on Rebooting Computing, Dec. 2015.
  37. L. Amaru, P.-E. Gaillardon, S. Mitra and G. De Micheli, “New Logic Synthesis as Nanotechnology Enabler,” Proceedings of the IEEE, 2015.
  38. M. Shavezipur, K. Harrison, W. S. Lee, S. Mitra, H.-S.P. Wong and R. T. Howe, “Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays,” Journal of Microelectromechanical Systems, Vol. 24, No. 3, pp. 592-598, June 2015.
  39. G. Hills, J. Zhang, M. Shulaker, H. Wei, C.-S. Lee, A. Balasingam, H.-S.P. Wong and S. Mitra, “Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations,” IEEE Trans. CAD, 2015.
  40. S. Mitra, H.-S.P. Wong, and S. Wong, “The Trojan-Proof Chip,” IEEE Spectrum, Feb. 2015 (Invited).
  41. L. Wanner, L. Lai, A. Rahimi, M. Gottscho, P. Mercati, C.-H. Huang, F. Sala, Y. Agarwal, L. Dolecek, N. Dutt, P. Gupta, R. Gupta, R. Jhala, R. Kumar, S. Lerner, S. Mitra, A. Nicolau, T. Rosing, M. Srivastava, S. Swanson, D. Sylvester and Y. Zhou, “NSF expedition on variability-aware software: Recent results and contributions,” IT Information Technology, Vol. 57, No. 3, pp. 181-198, 2015.
  42. D. Lin, T. Hong, Y. Li, Eswaran S., S. Kumar, F. Fallah, N. Hakim, D.S. Gardner and S. Mitra, “Effective Post-Silicon Validation of System-on-Chips using Quick Error Detection,” IEEE Trans. CAD, Oct. 2014. 
  43. M. Shulaker, J. Van Rethy, T. Wu, L. Liyanage, H. Wei, Z. Li, E. Pop, G. Gielen, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Circuit Integration up to sub-20nm Channel Lengths,” ACS Nano, 2014. 
  44. M Snir, RW Wisniewski, JA Abraham, SV Adve, S Bagchi, P Balaji, J Belak, P Bose, F Cappello, B Carlson, AA Chien, P Coteus, NA Debardelen, P Diniz, C Engelmann, M Erez, S Fazzari, A Geist, R Gupta, F Johnson, S Krishnamoorthy, S Leyffer, D Liberty, S Mitra, T Munson, R Schreiber, J Stearley, and EV Hensbergen, "Addressing Failures in Exascale Computing," The International Journal of High Performance Computing Application, Vol 28, Issue 2, pp. 127 - 171, May 2014.
  45. M. Shulaker, J. Van Rethy, G. Hills, H. Wei, H. Chen, G. Gielen, H.-S.P. Wong and S. Mitra, “Sensor-to-Digital Interface Built Entirely with Carbon Nanotube FETs,” IEEE Journal on Solid-State Circuits, Special Issue on IEEE Intl. Solid-State Circuits Conf., Jan. 2014 (Invited). 
  46. S. Bobba, J. Zhang, P.-E. Gaillardon, H.-S.P. Wong, S. Mitra and G. De Micheli, “System-Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits,” ACM Journal on Emerging Technologies in Computing Systems, 2014. 
  47. M. Shulaker, G. Hills, N. Patil, H. Wei, H. Chen, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Computer,” Nature, Vol. 501, No. 7468, Sept. 2013 (Special Cover Feature by Nature). 
  48. P. Gupta, M. Srivastava, Y. Agarwal, S. Swanson, D. Sylvester, R. Kumar, S. Mitra, N. Dutt, T. Simunic-Rosing and R. Gupta, “Underdesigned and Opportunistic Computing,” Keynote paper, IEEE Trans. CAD, 2013. 
  49. D. Lee, W.S. Lee, C. Chen, F. Fallah, J. Provine, S. Chong, J. Watkins, R.T. Howe, H.-S.P. Wong and S. Mitra, “Combinational Logic Design using Six-Terminal NEM Relays,” IEEE Trans. CAD, 2013. 
  50. R. Parsa, W.S. Lee, M. Shavezipur, J. Provine, R. Maboudian, S. Mitra, H.-S.P. Wong and R.T. Howe, "Laterally Actuated Platinum-Coated Polysilicon NEM Relays," Journal of Microelectromechanical Systems, vol. 22, no. 3, pp. 768-778, June 2013.
  51. J. Zhang, L. Wei, N. Patil, A. Lin, H. Wei, H.-S.P. Wong and S. Mitra, “Robust Digital VLSI using Carbon Nanotubes,” Keynote paper, IEEE Trans. CAD, 2012. 
  52. H. Cho, L. Leem and S. Mitra, “ERSA: Error Resilient System Architecture for Probabilistic Applications,” IEEE Trans. CAD, 2012. 
  53. L. S. Liyanage, H. Lee, N. Patil, S. Park, S. Mitra, Z. Bao and H. -S.P. Wong, “Wafer-Scale Fabrication and Characterization of Thin-Film Transistors with Polythiophene-Sorted Semiconducting Carbon Nanotube Networks,” ACS Nano, 6, pp. 451-458, 2012.
  54. M. Shulaker, H. Wei, N. Patil, J. Provine, H. Chen, H.-S.P. Wong and S. Mitra, “Linear Increases in Carbon Nanotube Density Through Multiple Transfer Technique,” Nanoletters, 2011. 
  55. S. Mitra, K. Brelsford, Y. Kim, K. Lee and Y. Li, “Robust System Design to Overcome CMOS Reliability Challenges,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on the IEEE CAS Forum on Emerging and Selected Topics, 2011 (Invited). 
  56. J. Zhang, N. Patil, A. Hazeghi, H.-S.P. Wong and S. Mitra, “Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations,” IEEE Trans. CAD, 2011. 
  57. S. Mitra, H. Cho, T. Hong, Y. Kim, H. Lee, L. Leem, Y. Li, D. Lin, E. Mintarno, S. Park, N. Patil, H. Wei and J. Zhang, “Robust System Design,” IPSJ Trans. System LSI Design Methodology, 2011 (Invited). 
  58. E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R.W. Dutton and S. Mitra, “Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging,” IEEE Trans. CAD, 2011. 
  59. J. Ousterhout, P. Agrawal, D. Erickson, C. Kozyrakis, J. Leverich, D. Mazieres, S. Mitra, A. Narayanan, D. Ongaro, G. Parulkar, M. Rosenblum, S. Rumble, E. Stratmann, R. Strutsman, “The Case for RAMCloud,” Communications of the ACM, pp. 121-130, July 2011.
  60. J. Opatkiewicz, M. C. LeMieux, N. P. Patil, H. Wei, S. Mitra and Z. Bao, "The effect of amine protonation on the electrical properties of spin-assembled single-walled carbon nanotube networks", Nanotechnology, 22, 2011.
  61. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong and S. Mitra, “Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mis-positioned Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2010. 
  62. A. Lin, N. Patil, J. Zhang, H. Wei, S. Mitra and H.-S.P. Wong, “ACCNT - A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines,” IEEE Trans. Electron Devices, 2010. 
  63. I. Loi, F. Angiolini, S. Mitra, S. Fujita and L. Benini, “Characterization and Implementation of Fault-Tolerant Vertical Links for 3D Networks-on-Chip,” IEEE Trans. CAD, 2010. 
  64. S. Park and S. Mitra, “Post-Silicon Bug Localization for Processors,” Research Highlight, Communications of the ACM, Feb. 2010 (Invited). 
  65. J. Ousterhout, P. Agrawal, D. Erickson, C. Kozyrakis, J. Leverich, D. Mazieres, S. Mitra, A. Narayanan, D. Ongaro, G. Parulkar, M. Rosenblum, S. Rumble, E. Stratmann, R. Strutsman, “The Case for RAMCloud: scalable high-performance storage entirely in DRAM,” ACM SIGOPS Operating Systems Review, pp. 92-105, Jan. 2010.
  66. S. Park, T. Hong and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE Trans. CAD , 2009. 
  67. Y. Li, Y.M. Kim, E. Mintarno, D. Gardner and S. Mitra, “Overcoming Early-Life Failure and Aging Challenges for Robust System Design,” IEEE Design and Test of Computers, Special Issue on Design for Reliability and Robustness, 2009 (Invited). 
  68. A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, “ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Concepts and Experimental Demonstration,” IEEE Trans. Electron Devices , 2009. 
  69. J. Zhang, N. Patil and S. Mitra, “Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,” IEEE Trans. CAD , 2009. 
  70. T. Chen, C. Ito, W. Loh, W. Wang, K. Doddapaneni, S. Mitra and R.W. Dutton, “Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies,” IEEE Trans. Electron Devices, 2009. 
  71. N. Patil, A. Lin, E. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S.P. Wong and S. Mitra, “Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2009. 
  72. N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, “Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, 2009. 
  73. K. Ryu, A. Badmaev, C. Wang, A. Lin, N. Patil, L. Gomez, A. Kumar, S. Mitra, H.-S.P. Wong and C. Zhou, “CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes,” Nanoletters, Vol. 9, Issue 1, pp 189–197, Jan. 2009. 
  74. M. LeMieux, S. Sok, M. Roberts, J. Opatkiewicz, D. Liu, S. barman, N. Patil, S. Mitra and Z. Bao, “Solution assembly of organized carbon nanotube networks for thin-film transistors,” ACS Nano, 3, 4089-4097, 2009.
  75. A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, “Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs,” IEEE Trans. Nanotechnology, 2009. 
  76. N. Patil, J. Deng, A. Lin, H.S.-P. Wong and S. Mitra, “Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits,” IEEE Trans. Computer-Aided Design, 2008. 
  77. C. Wang, K. Ryu, A. Badmaev, N. Patil, A. Lin, S. Mitra, H.-S. P. Wong and C. Zhou, “Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes,” Applied Physics Letters, 93, 033101 , 2008. 
  78. N. Shanbhag, S. Mitra, G. de Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, J. Rabaey , “In Search of Alternative Computational Paradigms,” IEEE Design and Test of Computers, 2008. 
  79. R. Kapur, S. Mitra, and T.W. Williams, “Historical Perspective of Scan Compression,” IEEE Design and Test of Computers, 2008 (Invited). 
  80. M. Zhang, S. Mitra, TM Mak, N. Seifert, Q. Shi, K.S. Kim, N. Shanbhag, N. Wang and S.J. Patel, “Sequential Element Design with Built-In Soft Error Resilience,” IEEE Trans. VLSI, Dec. 2006. 
  81. M. Tahoori and S. Mitra, “Application-Dependent Delay Testing of FPGAs,” IEEE Trans. CAD, 2006. 
  82. S. Mitra, N. Seifert, M. Zhang, Q. Shi and K.S. Kim, “Robust System Design with Built-In Soft Error Resilience,” IEEE Computer, Vol. 38, Number 2, pp. 43-52, Feb. 2005.
  83. S. Mitra and K.S. Kim, “XPAND: An Efficient Test Stimulus Compression Technique,” IEEE Trans. Computers, Special Issue on System-on-Chip Design and Test, 2006.
  84. S. Mitra, S. Lumetta, M. Mitzenmacher and N. Patil, “X-Tolerant Test Response Compaction,” IEEE Design and Test of Computers, Special Section on the 2005 International Test Conference, Nov.-Dec. 2005.
  85. R.K. Iyer, N. Nakka, Z. Kalbarczyk and S. Mitra, “Recent Advances in Hardware-Level Reliability Support for Transient Errors,” IEEE MICRO, Special Issue on the Reliability-Aware Microarchitectures, Nov.-Dec. 2005.
  86. M. Tahoori and S. Mitra, “Application Independent Testing of FPGA Interconnects,” IEEE Trans. CAD, Nov. 2005.
  87. A. Al-Yamani, S. Mitra and E.J. McCluskey, “Optimized Reseeding by Seed Ordering and Encoding,” IEEE Trans. CAD, Feb. 2005.
  88. S. Mitra, W. Huang. N.R. Saxena, S. Yu and E.J. McCluskey, “Reconfigurable Architecture for Autonomous Self-Repair,” IEEE Design & Test of Computers, Special Issue on Yield & Reliability, Vol. 21, Issue 3, pp. 228-240, May-June 2004.
  89. S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Trans. Computer-Aided Design, Vol. 23, Issue 3, pp. 421-432, March 2004.
  90. S. Mitra, N.R. Saxena, and E.J. McCluskey, “Efficient Design Diversity Estimation for Combinational Circuits,” IEEE Trans. Comp., Vol. 53, Issue 11, pp. 1,483-1,492, Nov. 2004.
  91. M. Tahoori and S. Mitra, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations,” IEEE Trans. Computer-Aided Design, Vol. 23, Issue 2, pp. 261-272, Feb. 2004.
  92. K.S. Kim, S. Mitra and P.G. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design and Test of Computers, Special Issue on Speed Test and Speed Binning of Complex ICs, Vol. 20, Issue 5, pp. 8-16, Sept.-Oct. 2003.
  93. S. Mitra, N.R. Saxena and E.J. McCluskey, “A Design Diversity Metric and Analysis of Redundant Systems,” IEEE Trans. Computers, Vol. 51, Issue 5, pp. 498-510, May 2002.
  94. N.S. Oh, S. Mitra and E.J. McCluskey, “ED44I: Error Detection by Diverse Data and Duplicated Instructions,” IEEE Trans. on Computers, Special Issue on Fault-Tolerant Embedded Systems, Vol. 51, Issue 2, pp. 180-199, Feb. 2002.
  95. S. Mitra, N.R. Saxena and E.J. McCluskey, “Common-Mode Failures in Redundant VLSI Systems: A Survey,” IEEE Trans. Reliability, Special Issue on Fault-Tolerant VLSI Systems, Vol. 49, Issue 3, pp. 285-295, Sept. 2000.
  96. S. Mitra, L.J. Avra and E.J. McCluskey, “Efficient Multiplexer Synthesis,” IEEE Design and Test of Computers, Vol. 17, No. 4, pp. 90-97, Oct. – Dec. 2000.
  97. N.R. Saxena, S. Gomez, W. Huang, S. Mitra, S. Yu and E.J. McCluskey, “Dependable Computing and On-Line Testing in Adaptive and Reconfigurable Systems,” IEEE Design and Test of Computers, Special Issue on Reconfigurable Computing, Vol. 17, No. 1, pp. 29-41, Jan. – Mar. 2000.
  98. S. Mitra, L.J. Avra and E.J. McCluskey, “An Output Encoding Problem and a Solution Technique,” IEEE Trans. Computer-Aided Design, Vol. 18, No. 6, pp. 761-768, June 1999.


Conference Publications:

  1. S. Chattopadhyay, K. Devarajegowda, F. Lonsing, B. D'Agostino, I. Vavelidou, V. Bhatt, S. Prebeck, W. Ecker, C. Trippel, C. Barrett and S. Mitra, “G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators,” ACM/IEEE Design Automation Conf., July 2023.
  2. D. Rich, A. Kasperovich, M. Malakoutian, R. Radway, S. Hagiwara, T. Yoshikawa, S. Chowdhury and S. Mitra, “Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits,” ACM/IEEE Design Automation Conf., July 2023.
  3. T. Srimani, A.C. Yu, R. Radway, D. Rich, M. Nelson, S. Wong, D. Murphy, S. Fuller, G. Hills, S. Mitra and M. Shulaker, “Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM,” Symp. VLSI Technology, June 2023.
  4. G. Pitner, N. Safron, T.-A. Chao, S. Li, S.-K. Su, G. Zeevi, Q. Lin, H.-Y. Chiu, M. Passlack, Z. Zhang, D.M. Sathaiya, A. Wei, C. Gilardi, E. Chen, S.-L. Liew, V. D.-H. Hou, C.-C. Wu, J. Wu, Z. Lin, J. Fagan, M. Zheng, H. Wang, S. Mitra, H.-S.P. Wong and I. Radu “Building High-Performance Transistors on Carbon Nanotube Channel: Tradeoffs and Progress on Modules,” Symp. VLSI Technology, June 2023.
  5. T. Srimani, R.M. Radway, J. Kim, K. Prabhu, D. Rich, C. Gilardi, P. Raina, M. Shulaker, S.K Lim and S. Mitra, “Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits,” ACM/IEEE Design Automation and Test in Europe, April 2023.
  6. A. Lotlikar, N.P. Shah, A.R. Gogliettino, R. Vilkhu, S. Madugula, L. Grosberg, P. Hottowy, A. Sher, A. Litke, E.J. Chichilnisky and S. Mitra, “Partitioned Temporal Dithering for Efficient Epiretinal Electrical Stimulation,” IEEE/EMBS Intl. Conf. Neural Engineering, April 2023.
  7. P.K. Vasireddy, A.R. Gogliettino, J.B. Brown, R.S. Vilkhu, S. Madugula, A.J. Phillips, S. Mitra, P. Hottowy, A. Sher, A. Litke, N.P. Shah and E.J. Chichilnisky, “Efficient Modeling and Calibration of Multi-Electrode Stimuli for Epiretinal Implants,” IEEE/EMBS Intl. Conf. Neural Engineering, April 2023.
  8. W. Li, C. Nigh, D. Duvalsaint, R.D. Blanton and S. Mitra, “PEPR: Pseudo-Exhaustive Physically-Aware Region Testing,” IEEE Intl. Test Conf., Sept. 2022.
  9. R.M. Radway, K. Sethi, W.-C. Chen, J. Kwon, S. Liu, T.F. Wu, E. Beigne, M.M. Shulaker, H.-S.P. Wong and S. Mitra, “The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design,” IEEE Intl. Electron Devices Meeting, Dec. 2021 (Invited).
  10. C. Gilardi, B. Chehab, G. Sisto, P. Schuddinck, Z. Ahmed, O. Zografos, Q. Lin, G. Hellings, J. Ryckaert, H.-S.P. Wong and S. Mitra, “Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization,” IEEE Intl. Electron Devices Meeting, Dec. 2021.
  11. S. Chattopadhyay, F. Lonsing, L. Piccolboni, D. Soni, P. Wei, X. Zhang, Y. Zhou, L. Carloni, D. Chen, J. Cong, R. Karri, Z. Zhang, C. Trippel, C. Barrett and S. Mitra, “Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition,” Formal Methods in Computer-Aided Design, Oct. 2021.
  12. M. Giordano, K. Prabhu, K. Koul, R. Radway, A. Gural, R. Doshi, Z. Khan, J. Kustin, T. Liu, G. Lopes, V. Turbiner, W-S. Khwa, Y-D. Chih, M-F. Chang, G. Lallement, B. Murmann, S. Mitra and P. Raina, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” Symp. VLSI Circuits, June 2021.
  13. G. Pitner, Z. Zhang, Q. Lin, S.-K Su, C. Gilardi, C. Kuo, H. Kashyap, T. Weiss, Z. Yu, T.-A. Chao, L.-J. Li, S. Mitra, H.-S. P. Wong, J. Cai, A. Kummel, P. Bandaru and M. Passlack, “Sub-0.5 nm Interfacial Dielectric Enables Superior Electrostatics: 65 mV/dec Top-Gated Carbon Nanotube FETs at 15 nm Gate Length,” IEEE Intl. Electron Devices Meeting, Dec. 2020.
  14. E. Esmanhotto, L. Brunet, N. Castellani, D. Bonnet, T. Dalgaty, L. Grenouillet, D. Ly, C. Cagli, C. Vizioz, N. Allouti, F. Laulagnet, O. Gully, N. Bernard-Henriques, M. Bocquet, G. Molas, P. Vivet, D. Querlioz, JM. Portal, S. Mitra, F. Andrieu, C. Fenouillet-Beranger, E. Nowak and E. Vianello, “High-Density 3D Monolithically Stacked 1T1R Multi-Level-Cell for Neural Networks,” IEEE Intl. Electron Devices Meeting, Dec. 2020.
  15. F. Lonsing, S. Mitra and C. Barrett, “A Theoretical Framework for Symbolic Quick Error Detection,” Formal Methods in Computer-Aided Design, Sept. 2020.
  16. R. Gauchi, V. Egloff, M. Kooli, J.-P. Noel, B. Giraud, P. Vivet, S. Mitra and H.-P. Charles, “Reconfigurable Tiles of Computing-In-Memory SRAM Architecture for Scalable Vectorization,” ACM/IEEE Intl. Symp. Low-Power Electronics and Design, August 2020.
  17. E. Singh, F. Lonsing, S. Chattopadhyay, M. Strange, P. Wei, X. Zhang, Y. Zhou, J. Cong, D. Chen, Z. Zhang, P. Raina, C. Barrett and S. Mitra, “A-QED Verification of Hardware Accelerators,” ACM/IEEE Design Automation Conf., San Francisco, CA, July 2020.
  18. J. Chen, M. Zaman, Y. Makris, S. Blanton, S. Mitra and B. Carrion Schafer, “DECOY: Deflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual Property,” ACM/IEEE Design Automation Conf., San Francisco, CA, July 2020.
  19. M. Fadiheh, J. Muller, R. Brinkmann, S. Mitra, D. Stoffel and W. Kunz, “A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-order Processors,” ACM/IEEE Design Automation Conf., San Francisco, CA, July 2020.
  20. K. Devarajegowda, M. Fadiheh, E. Singh, C. Barrett, S. Mitra, W. Ecker, D. Stoffel and W. Kunz, “Gap-free Processor Verification by S²QED and Property Generation,” ACM/IEEE Design Automation and Test in Europe, Grenoble, France, March 2020.
  21. E.R. Hsieh, M. Giordano, B. Hodson, A. Levy, S.K. Osekowsky, R.M. Radway, Y.C. Shih, W. Wan, T.F. Wu, X. Zheng, M. Nelson, B.Q. Le, H.-S.P. Wong, S. Mitra and S. Wong, “High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning,” IEEE Intl. Electron Devices Meeting, San Francisco, CA, Dec. 2019.
  22. F. Lonsing, K. Ganesan, M. Mann, S.S. Nuthakki, E. Singh, M. Srouji, Y. Yang, S. Mitra and C. Barrett, “Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED,” IEEE/ACM Intl. Conf. Computer-Aided Design, Westminster, CO, Nov. 2019 (Invited).
  23. R. Gauchi, M. Kooli, P. Vivet, J.-P. Noël, E. Beigné, S. Mitra and H.-P. Charles, “Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture,” IEEE/IFIP Intl. Conf. VLSI-SoC, Oct. 2019.
  24. E. Cheng, D. Mueller-Gritschneder, J. Abraham, P. Bose, A. Buyuktosunoglu, D. Chen, H. Cho, Y. Li, U. Sharif, K. Skadron, M. Stan, U. Schlichtmann and S. Mitra, “Cross-Layer Resilience: Challenges, Insights, and the Road Ahead,” IEEE/ACM Design Automation Conf., Las Vegas, NV, June 2019 (Invited).
  25. D. Muratore, P. Tandon, M. Wootters, E.J. Chichilnisky, S. Mitra and B. Murmann, “A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording,” IEEE Intl. Symp. Circuits and Systems, Sapporo, Japan, May 2019.
  26. N.P. Shah, S. Madugula, L. Grosberg, G. Mena, P. Tandon, P. Hottowy, A. Sher, A.M. Litke, S. Mitra and E.J. Chichilnisky, “Optimization of Electrical Stimulation for a High-Fidelity Artificial Retina,” IEEE EMBS Conf. Neural Engineering, San Francisco, CA, March 2019.
  27. E. Singh, K. Devarajegowda, S. Simon, R. Schnieder, K. Ganesan, M. Fadiheh, D. Stoffel, W. Kunz, C. Barrett, W. Ecker and S. Mitra, “Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study,” IEEE/ACM Design Automation and Test in Europe, Florence, Italy, March 2019.
  28. M. Fadiheh, D. Stoffel, C. Barrett, S. Mitra and W. Kunz, “Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking,” IEEE/ACM Design Automation and Test in Europe, Florence, Italy, March 2019.
  29. G. Gielen, N. Xama, K. Ganesan and S. Mitra, “Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SoCs,” IEEE/ACM Design Automation and Test in Europe, Florence, Italy, March 2019.
  30. T. Wu, B. Le, R. Radway, A. Bartolo, W. Hwang, S. Jeong, H. Li, P. Tandon, E. Vianello, P. Vivet, E. Nowak, M. Wootters, H.-S.P. Wong, M. Aly, E. Beigne and S. Mitra, “A 43pJ/cycle Non-volatile Microcontroller with 4.7µs Shutdown/Wake-up integrating 2.3 bits-per-cell Resistive RAM and Resilience Techniques,” IEEE Intl. Solid-State Circuits Conf., San Francisco, CA, 2019.
  31. G. Hills, D. Bankman, B. Moons, L. Yang, J. Hillard, A. Kahng, R. Park, M. Verhelst, B. Murmann, M. Shulaker, H.-S.P. Wong and S. Mitra, “TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration using Carbon Nanotube FETs,” IEEE/ACM Design Automation Conf., San Francisco, CA, 2018.
  32. W. Hwang, W. Wan, S. Mitra, and H.-S.P. Wong, “Coming up N3XT, After 2D Scaling of Si CMOS,” IEEE Intl. Symp. Circuits and Systems, Florence, Italy, May 2018 (Invited).
  33. M. Fadiheh, J. Urdahl, S. Nuthakki, C. Barrett, S. Mitra, D. Stoffel and W. Kunz, “Symbolic Quick Error Detection with Symbolic Initial State for Pre-Silicon Verification,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2018.
  34. D. Mueller-Gritschneder, M. Dittrich, J. Weinzierl, E. Cheng, S. Mitra and U. Schlichtmann, “ETISS-ML: A Multi-Level Instruction Set Simulator with RTL-level Fault Injection Support for the Evaluation of Cross-Layer Resiliency Techniques,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2018.
  35. T. Wu, P.-C. Huang, A. Rahimi, H. Li, M. Shulaker, J. Rabaey, H.-S.P. Wong and S. Mitra, “Brain-Inspired Computing Exploiting Carbon Nanotube FETs and Resistive RAM: Hyperdimensional Computing Case Study,” IEEE Intl. Solid-State Circuits Conf., San Francisco, CA, Feb. 2018.
  36. E. Cheng, J. Abraham, P. Bose, A. Buyuktosunoglu, K. Campbell, D. Chen, C.-Y. Cher, H. Cho, B. Le, K. Lilja, S. Mirkhani, K. Skadron, M. Stan, L. Szafaryn, C. Vezyrtzis and S. Mitra, “Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights,” IEEE Intl. Conf. Computer Design, Boston, MA, Oct. 2017 (Invited).
  37. W. Hwang, M. Aly, Y. Malviya, M. Gao, T. Wu, C. Kozyrakis, H.-S.P. Wong and S. Mitra, “3D Nanosystems Enable Embedded Abundant-Data Computing,” IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, Seoul, South Korea, Oct. 2017 (Invited).
  38. E. Singh, C. Barrett and S. Mitra, “E-QED: Electrical Bug Localization during Post-Silicon Validation Enabled by Quick Error Detection and Formal Methods,” Intl. Conf. Computer-Aided Verification, Heidelberg, Germany, July 2017.
  39. A.D. Patil, N.R. Shanbhag, L. Varshney, E. Pop, H.-S.P. Wong, S. Mitra, J. Rabaey, J. Weldon, L. Pileggi, S. Manipatruni, D. Nikonov and I.A. Young, “A Systems Approach to Computing in Beyond CMOS Fabrics,” IEEE/ACM Design Automation Conf., Austin, TX, June 2017 (Invited).
  40. H. Li, T. Wu, S. Mitra and H.-S.P. Wong, “Device-Architecture Co-Design for Hyperdimensional Computing with 3D Vertical Resistive Switching Random Access Memory (3D VRRAM),” Intl. Symp. VLSI Technology, Systems and Applications, Hsinchu, Taiwan, April 2017 (Invited).
  41. H. Li, T. Wu, A. Rahimi, K-S. Li, M. Rusch, C-H. Lin, J-L. Hsu, M.M. Sabry, S. Eryilmaz, J. Sohn, W-C Chiu, M-C. Chen, T-T. Wu, J-M. Shieh, W-K. Yeh, J.M. Rabaey, S. Mitra and H.-S.P. Wong, “Hyperdimensional Computing with 3D VRRAM In-Memory Kernels: Device-Architecture Co-Design for Energy-Efficient, Error-Resilient Language Recognition,” IEEE Intl. Electron Devices Meeting, San Francisco, CA, Dec. 2016.
  42. E. Cheng, S. Mirkhani, L. Szafaryn, C.-Y. Cher, H. Cho, K. Skadron, M. Stan, K. Lilja, J. Abraham, P. Bose and S. Mitra, “CLEAR: Cross-Layer Exploration for Architecting Resilience: Combining Hardware and Software Techniques To Tolerate Soft Errors in Processor Cores,” IEEE/ACM Design Automation Conference, Austin, TX, June 2016.
  43. R. Braojos, M. Aly, T. Wu, G. Ansaloni, H.-S.P. Wong, S. Mitra and D. Atienza, “Nano-Engineered Architectures for Ultra-Low Power Wireless Body Sensor Nodes,” IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis,, Pittsburgh, PA, Oct. 2016.
  44. A.A. Sharma, Y. Kesim, M. Shulaker, C. Kuo, C. Augustine, H.-S. P. Wong, S. Mitra, M. Skowronski, J. A. Bain and J. A. Weldon, “Low-power, High-performance S-NDR Oscillators for Stereo (3D) Vision using Directly-Coupled Oscillator Networks,” Symp. VLSI Tech., Honolulu, HI, June 2016.
  45. M. Shulaker, G. Hills, M. Giachino, T. Wu, Z. Bao, H.-S.P. Wong and S. Mitra, “Efficient Carbon Nanotube Removal for Highly-Scaled Technologies,” IEEE Intl. Electron Devices Meeting, Washington DC, Dec. 2015.
  46. D. Lin, E. Singh, C. Barrett and S. Mitra, “A Structured Approach to Post-Silicon Validation and Debug using Symbolic Quick Error Detection,” IEEE International Test Conf., Anaheim, CA, Oct. 2015.
  47. K. Campbell, D. Lin, D. Chen and S. Mitra, “H-QED: Fast and Effective Post-Silicon Validation and Debug of Hardware Accelerators Through Hybrid Quick Error Detection,” IEEE/ACM Design Automation Conference, San Francisco, CA, June 2015.
  48. H. Cho, C.-Y. Cher, T. Shepherd and S. Mitra, “Understanding Soft Errors in Uncore Components,” IEEE/ACM Design Automation Conference, San Francisco, CA, June 2015.
  49. A.A. Sharma, T.C. Jackson, M. Shulaker, C. Kuo, C. Augustine, J. A. Bain, H.-S. P. Wong, S. Mitra, L.T. Pileggi and J. A. Weldon, “High Performance, Integrated 1T1R Oxide-Based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications,” Symp. VLSI Tech., Kyoto, Japan, June 2015.
  50. D. Lin, Eswaran S., S. Kumar, E. Rentschler and S. Mitra, “Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug,” IEEE/ACM Design Automation and Test in Europe, Grenoble, France, March 2015.
  51. M. Shulaker, T. Wu, M. Sabry, H. Wei, H.-S.P. Wong and S. Mitra, “Monolithic 3D Integration: A Path From Concept To Reality,” IEEE/ACM Design Automation and Test in Europe, Grenoble, France, March 2015 (Invited).
  52. S. Mirkhani, C.-Y. Cher, S. Mitra and J.A. Abraham, Efficient Soft Error Vulnerability Estimation for Complex Designs,” IEEE/ACM Design Automation and Test in Europe, Grenoble, France, March 2015.
  53. G. Gielen, J. Van Rethy, M. Shulaker, G. Hills, H.-S.P. Wong and S. Mitra, “Time-Based Sensor Interface Circuits in Carbon Nanotube Technology,” IEEE Intl. Symp. Circuits and Systems, Lisbon, Portugal, May 2015 (Invited).
  54. L. Amaru, G. Hills, P.-E. Gaillardon, S. Mitra and G. De Micheli, “Multiple Independent Gate FETs: How Many Gates Do We Need?,” IEEE Asia and South Pacific Design Automation Conf., Tokyo, Japan, Jan. 2015.
  55. M. Shulaker, G. Pitner, G. Hills, M. Giachino, H.-S.P. Wong and S. Mitra, “High-Performance Carbon Nanotube Field-Effect Transistors,” IEEE Intl. Electron Devices Meeting, San Francisco, CA, Dec. 2014.
  56. M. Shulaker, T. Wu, A. Pal, K. Saraswat, H.-S.P. Wong and S. Mitra, “Monolithic 3D Integration of Carbon Nanotube FETs, Resistive RAM, and Silicon FETs,” IEEE Intl. Electron Devices Meeting, San Francisco, CA, Dec. 2014.
  57. G. Hills, M. Shulaker, H. Wei, H. Chen, H.-S.P. Wong and S. Mitra, “Robust Design and Experimental Demonstrations of Carbon Nanotube Digital Circuits," IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 2014 (Invited).
  58. M. Shulaker, K. Saraswat, H.-S.P. Wong and S. Mitra, “Three-Dimensional Integration of Carbon Nanotube FETs with Silicon CMOS," Symp. VLSI Tech, Honolulu, HI, June 2014.
  59. S. Mitra, P. Bose, E. Cheng, H. Cho, R. Joshi, Y.M. Kim, C. Lefurgy, Y. Li, K. Rodbell, K. Skadron, J. Stathis and L. Szafaryn, “The Resilience Wall: Cross-Layer Solution Strategies," IEEE Intl. Symp. VLSI Technology, Systems and Applications and IEEE Intl. Symp. VLSI Design, Automation and Test, Hsinchu, Taiwan, April 2014 (Invited).
  60. D. Lin and S. Mitra, “QED Post-Silicon Validation and Debug: Frequently Asked Questions," IEEE Asia and South Pacific Design Automation Conference, Singapore, Jan. 2014 (Invited).
  61. S. Mirkhani, H. Cho, S. Mitra and J. Abraham, “Rethinking Error Injection for Effective Resilience," IEEE Asia and South Pacific Design Automation Conference, Singapore, Jan. 2014 (Invited).
  62. H. Wei, M. Shulaker, H.-S.P. Wong and S. Mitra, “Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits," IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2013.
  63. Y. Li, E. Cheng, S. Makar and S. Mitra, “Self-Repair of Uncore Components in Robust System-on-Chips: An OpenSPARC T2 Case Study," IEEE Intl. Test Conf., Anaheim, CA, Sept. 2013.
  64. M. Sauer, Y.M. Kim, J. Seomun, H.-O. Kim, K.-T. Do, J.Y. Choi, K.S. Kim, S. Mitra and B. Becker, “Early-Life Failure Detection using SAT-Based ATPG," IEEE Intl. Test Conf., Anaheim, CA, Sept. 2013.
  65. Y.M. Kim, J. Seomun, H.-O. Kim, K.-T. Do, J.Y. Choi, K.S. Kim, M. Sauer, B. Becker and S. Mitra, “Detection of Early-Life Failures in High-K Metal-Gate Transistors and Ultra Low-K Inter-Metal Dielectrics," IEEE Custom Integrated Circuits Conf., San Jose, CA, Sept. 2013.
  66. H. Cho, S. Mirkhani, C.-Y. Cher, J.A. Abraham and S. Mitra, “Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design," IEEE/ACM Design Automation Conf., Austin, TX, June 2013.
  67. G. Hills, M. Shulaker, J. Zhang, H.-S.P. Wong and S. Mitra, “Rapid Exploration of Processing and Design Guidelines to Overcome Carbon Nanotube Variations," IEEE/ACM Design Automation Conf., Austin, TX, June 2013.
  68. M. Shulaker, J. Van Rethy, G. Hills, H. Chen, G. Gielen, H.-S.P. Wong and S. Mitra, “Sascha: The Stanford Carbon Nanotube Controlled Handshaking Robot," IEEE/ACM Design Automation Conf., Austin, TX, June 2013 (Invited).
  69. L.S. Liyanage, X. Chen, H. Wei, H.-Y. Chen, S. Mitra and H.-S.P. Wong, “Reliability of Graphene Interconnects and N-type Doping of Carbon Nanotube Transistors," IEEE Reliability Physics Symp., Monterey, CA, April 2013 (Invited).
  70. D. Lin, T. Hong, Y. Li, F. Fallah, D.S. Gardner, N. Hakim and S. Mitra, “Overcoming Post-Silicon Validation Challenges through Quick Error Detection (QED)," IEEE/ACM Design Automation and Test in Europe, Grenoble, France, March 2013 (Invited).
  71. H. Wei, M. Shulaker, G. Hills, H. Chen, C. Li, L. Liyanage, J. Zhang, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Circuits: Opportunities and Challenges," IEEE/ACM Design Automation and Test in Europe, Grenoble, France, March 2013 (Invited).
  72. M. Shulaker, J. Van Rethy, G. Hills, H. Chen, G. Gielen, H.-S.P. Wong and S. Mitra, “Experimental Demonstration of a Fully Digital Capacitive Sensor Interface Built Entirely using Carbon Nanotube FETs,” IEEE Intl. Solid-State Circuits Conf., San Francisco, CA, Feb. 2013.
  73. H. Wei, T. Wu, D. Sekar, B. Cronquist, F. Pease and S. Mitra, “Cooling Three-Dimesnional Integrated Circuits using Power Delivery Networks,” IEEE Intl. Electron Devices Meeting, San Francisco, CA, Dec. 2012.
  74. D. Lin, T. Hong, F. Fallah, N. Hakim and S. Mitra, “Quick Detection of Difficult Bugs for Effective Post-Silicon Validation,” IEEE/ACM Design Automation Conference, San Francisco, CA, June 2012.
  75. C. Chen, W.S. Lee, R. Parsa, S. Chong, J. Provine, J. Watt, R.T. Howe, H.-S.P. Wong and S. Mitra, “Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2012.
  76. H. Yi, X. Bao, J. Zhang, R. Tiberio, J. Conway, L. Chang, S. Mitra and H.-S.P. Wong, “Contact-Hole Patterning for Random Logic Circuits using Block Copolymer Directed Self-Assembly,” Proceedings of SPIE, San Jose, CA, February 2012.
  77. J. Zhang, N. Patil, H.-S.P. Wong and S. Mitra, “Overcoming Carbon Nanotube Variations through Co-optimized Technology and Circuit Design,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.
  78. H.-S.P. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei, J. Zhang, “Carbon Nanotube Electronics – Materials, Devices, Circuits, Design, Modeling, and Performance Projection,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011 (Invited).
  79. S. Chong, B. Lee, K. Parizi, J. Provine, S. Mitra, R. Howe and H.-S.P. Wong, “Integration of Nanoelectromechanical (NEM) Relays with Silicon CMOS with Functional CMOS-NEM Circuit,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.
  80. H. Wei, H. Chen, L. Liyanage, H.-S.P. Wong and S. Mitra, “Air-Stable Technique for Fabricating n-Type Carbon Nanotube FETs,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.
  81. H. Wei, J. Zhang, L. Wei, N. Patil, A. Lin, M. Shulaker, H. Chen, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated,” IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, November 2011.
  82. H. Chen, N. Patil, A. Lin, L. Wei, C. Beasley, J. Zhang, X. Chen, H. Wei, L.S. Liyanage, M. Shulaker, S. Mitra and H.-S.P. Wong, “Carbon Electronics – From Material Synthesis to Circuit Demonstration,” Intl. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, 2011 (Invited).
  83. L. Leem, H. Cho, Y.M. Kim, H. Lee, Y. Li and S. Mitra, “Cross-Layer Error Resilience for Robust Systems,” IEEE/ACM Intl. Conf. Computer-Aided Design, San Jose, CA, Nov. 2010 (Invited).
  84. T. Hong, Y. Li, S. Park, D. Mui, D. Lin, Z. Khaleq, N. Hakim, H. Naeimi, D. Gardner and S. Mitra, “QED: Quick Error Detection Tests for Effective Post-Silicon Validation,” IEEE International Test Conference, Austin, TX, Nov. 2010.
  85. S. Park, A.C. Bracy, H. Wang and S. Mitra, “BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010.
  86. J. Zhang, S. Bobba, N. Patil, A. Lin, H.-S.P. Wong, G. De Micheli and S. Mitra, “Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010.
  87. S. Mitra, S. Seshia and N. Nicolici, “Post-Silicon Validation: Opportunities, Challenges and Recent Advances,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010 (Invited).
  88. Y. Kim, Y. Kameda, H. Kim, M. Mizuno and S. Mitra, “Low-Cost Gate-Oxide Early-life Failure Detection in Robust Systems,” Symposium VLSI Circuits, Honolulu, Hawaii, June 2010.
  89. H. Wei, N. Patil, J. Zhang, A. Lin, H. Chen, H.-S.P. Wong and S. Mitra, “Efficient Metallic Carbon Nanotube Removal Readily Scalable to Wafer-Level VLSI CNFET Circuits,” Symposium VLSI Technology, Honolulu, Hawaii, June 2010.
  90. H. Lee, K. Lilja, M. Bounasser, P. Relangi, I. Linscott, U. Inan and S. Mitra, “LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design,” IEEE Intl. Reliability Physics Symposium, Anaheim, CA, May 2010.
  91. Y. Li, D. Gardner and S. Mitra, “Concurrent Autonomous Self-Test for Uncore Components in SoCs,” IEEE VLSI Test Symposium, Santa Cruz, CA, April 2010.
  92. Y. Kim, T. Chen, Y. Kameda, M. Mizuno and S. Mitra, “Gate-Oxide Early-life Failure Identification using Delay Shifts,” IEEE VLSI Test Symposium, Santa Cruz, CA, April 2010.
  93. J. Zhang, N. Patil, A. Lin, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Circuits: Living with Imperfections and Variations,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010 (Invited).
  94. S. Mitra, K. Brelsford and P. Sanda, “Cross-Layer Resilience Challenges: Metrics and Optimization,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010 (Invited).
  95. Y. Kanoria, A. Montanari and S. Mitra, “Statistical Static Timing Analysis using Markov Chain Monte Carlo,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.
  96. E. Mintarno, Y. Cao, S. Boyd, R. Dutton and S. Mitra, “Optimized Self-Tuning to Maximize Lifetime Energy-Efficiency in the Presence of Circuit Aging,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.
  97. L. Leem, H. Cho, J. Bau, Q. Jacobson and S. Mitra, “ERSA: Error-Resilient System Architecture for Probabilistic Applications,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.
  98. C. Chen, S. Chong, R. Parsa, N. Patil, K. Akarvardar, J. Provine, D. Lewis, J. Watt, R. Howe, H.-S.P. Wong and S. Mitra, “Efficient FPGAs using Nanoelectromechanical Relays,” ACM Intl. Symp. FPGA, Monterey, CA, Feb. 2010.
  99. S. Mitra, “Robust System Design,” IEEE Intl. Conf. VLSI Design, Bangalore, India, Jan. 2010 (Invited).
  100. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong and S. Mitra, “VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs,” IEEE Intl. Electron Devices Meeting, Baltimore, MD, Dec. 2009.
  101. H. Wei, N. Patil, A. Lin, H.-S.P. Wong and S. Mitra, “Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects,” IEEE Intl. Electron Devices Meeting, Baltimore, MD, Dec. 2009.
  102. Y. Li, O. Mutlu and S. Mitra, “Operating System Scheduling for Efficient On-line Self-Test in Robust Systems,” IEEE/ACM Intl. Conf. Computer-Aided Design, San Jose, CA, Nov. 2009.
  103. S. Chong, et al., “Nanoelectromechanical (NEM) Relay Integrated with CMOS SRAM for Improved Stability and Low Leakage,” IEEE/ACM Intl. Conf. Computer-Aided Design, San Jose, CA, Nov. 2009.
  104. R. Zheng, et al., “Circuit Aging Prediction for Low-Power Operation,” Custom Integrated Circuits Conf., San Jose, CA, Sept. 2009.
  105. N. Patil, A. Lin, J. Zhang, H.-S.P. Wong and S. Mitra, “Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions,” IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009 (Invited).
  106. J. Zhang, N. Patil, A. Hazeghi and S. Mitra, “Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations,” IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009.
  107. A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, “A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT),” VLSI Technology Symp., Kyoto, Japan, June 2009.
  108. S. Mitra, J. Zhang, N. Patil and H. Wei, “Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs,” IEEE/ACM Design Automation and Test in Europe (DATE), Nice, France, April 2009 (Invited).
  109. H. Baba and S. Mitra, “Testing for Transistor Aging,” IEEE VLSI Test Symp., Santa Cruz, CA, April 2009.
  110. T.W. Chen, Y.M. Kim, K. Kim, Y. Kameda, M. Mizuno and S. Mitra, “Experimental Study of Gate-Oxide Early Life Failures,” Intl. Reliability Physics Symp., Toronto, Canada, April 2009.
  111. H. Inoue, Y. Li and S. Mitra, “VAST: Virtualization Assisted Concurrent Autonomous Self-Test,” Intl. Test Conf., Santa Clara, CA, Oct. 2008.
  112. M. Agarwal, et al., “Optimized Circuit Failure Prediction for Aging: Practicality and Promise,” Intl. Test Conf., Santa Clara, CA, Oct. 2008.
  113. I. Loi, et al., “A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network-on-Chip Links,” Intl. Conf. CAD (ICCAD), San Jose, CA, Nov. 2008.
  114. N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, “Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symp. VLSI Technology, Honolulu, Hawaii, June 2008.
  115. S. Park and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE/ACM Design Automation Conf., Anaheim, CA, June 2008.
  116. S. Mitra, N. Patil and J. Zhang, “Imperfection-Immune Carbon Nanotube VLSI Logic Circuits,” Foundations of NANO (FNANO), Snowbird, UT, April 2008 (Invited).
  117. T.W. Chen, K. Kim, Y. Kim and S. Mitra, “Gate-Oxide Early Life Failure Prediction,” IEEE VLSI Test Symp., San Diego, CA, April 2008.
  118. Y. Li, S. Makar and S. Mitra, “CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns,” Design Automation and Test in Europe, Munich, Germany, March 2008.
  119. J. Zhang, N. Patil and S. Mitra, “Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits,” Design Automation and Test in Europe, Munich, Germany, March 2008.
  120. S. Mitra, “ Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges,” Design Automation and Test in Europe, Munich, Germany, March 2008 (Invited).
  121. S. Mitra, “Circuit Failure Prediction for Robust System Design in Scaled CMOS,” International Reliability Physics Symp., Phoenix, AZ, May 2008 (Invited).
  122. N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, San Diego, CA, June 2007.
  123. S. Mitra and M. Agarwal, “Circuit Failure Prediction to Overcome Scaled CMOS Reliability Challenges,” Intl. Test Conf., Santa Clara, CA, Oct. 2007 (Invited).
  124. M. Agarwal, B. Paul and S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symp., Berkeley, CA, April 2007.
  125. J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2007.
  126. P. Relangi and S. Mitra, “Erratic Bit Errors in Latches,” Intl. Reliability Physics Symp. (IRPS), Phoenix, AZ, April 2007.
  127. S. Seshia, W. Li and S. Mitra, “Verification Guided Soft Error Resilience,” Design Automation and Test in Europe (DATE), Nice, France, April 2007.
  128. T.W. Chen, C. Ito, W. Loh, W. Wang, S. Mitra and R.W. Dutton, “Marco-model for Post-breakdown 90nm and 130nm Transistors and its Applications in Predicting Chip-level Function Failure after ESD-CDM Events,” Intl. Reliability Physics Symp., Phoenix, AZ, April 2007.
  129. S. Mitra, M. Zhang, N. Seifert, TM Mak and K.S. Kim, “Built-In Soft Error Resilience for Robust System Design,” Intl. Conf. Integrated Circuit Design and Technology, Austin, TX, June 2007 (Invited).
  130. N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech, Orlando, FL, March 2007 (Invited).
  131. K.Y. Cho, S. Mitra and E.J. McCluskey, “California Scan: A Scan Architecture to Utilize Don't Care Bits in Test Patterns,” Intl. Test Conf., Santa Clara, CA, Oct. 2007.
  132. B. Mungamuru, H. Garcia Molina, and S. Mitra, “How to Safeguard your Sensitive Data,” Intl. Symp. Reliable Distributed Systems, 2006.
  133. J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).
  134. S. Mitra, M. Zhang, N. Seifert, T.M. Mak, and K.S. Kim, “Soft Error Resilient System Design through Error Correction,” IFIP SOC VLSI, 2006 (Invited).
  135. S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas and K.S. Kim, “Combinational Logic Soft Error Correction,” IEEE Intl. Test Conf., 2006.
  136. N.P. Patil, S. Mitra and S.S. Lumetta, “Signature Analyzer Design for Yield Learning Support,” IEEE Intl. Test Conf., 2006.
  137. M. Tahoori and S. Mitra, “Test Compression for FPGAs,” IEEE Intl. Test Conf., 2006.
  138. N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra and J. Maiz, “Radiation Induced Soft Error Rates of Advanced CMOS Bulk Devices,” IEEE Intl. Reliability Physics Symp., 2006.
  139. R. Guo, S. Mitra, J. Lee, S. Sivaraj and M. Ameen, "Comparison of Test Metrics: Stuck-at, N-Detect and Gate-Exhaustive," IEEE VLSI Test Symp., 2006.
  140. S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia and K.S. Kim, “Logic Soft Errors: A Major Barrier to Robust Platform Design,” Intl. Test Conf., 2005.
  141. D.J. Leavins, K.S. Kim, S. Mitra and E. Rodriguez, “Robust Platform Design in Sub-65nm Technologies,” Custom Integrated Circuits Conference, 2005, (Invited).
  142. Z. Stanojevic. R. Guo, S. Mitra and S. Venkataraman, “Enabling Yield Analysis with X-Compact,” Intl. Test Conf., 2005.
  143. K.Y. Cho, S. Mitra and E.J. McCluskey, “Gate Exhaustive Testing,” Intl. Test Conf., 2005.
  144. S. Mitra, T. Karnik, N. Seifert and M. Zhang, “Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges,” Design Automation Conf., 2005.
  145. T.M. Mak, S. Mitra and M. Zhang, “DFT Assisted Built-In Soft Error Resilience,” IEEE Intl. On-line Test Symp., 2005, (Invited).
  146. S. Mitra, “Built-In Soft Error Resilience Techniques,” IEEE VLSI Test Symp., 2005, (Invited).
  147. S. Mitra, K.S. Kim, T.M. Mak, N. Seifert, P. Shipley, M. Zhang and V. Zia, “Built-In Soft Error Resilience Structures,” Intel Design and Test Technology Conference, 2005.
  148. Z. Stanojevic, R. Guo, S. Mitra and S. Venkataraman, “Fault Diagnosis with X-Compact,” Intel Design and Test Technology Conference, 2005.
  149. E. Volkerink and S. Mitra, “Test Response Compression with Any Number of Unknowns,” Design Automation Conference, 2005.
  150. S. Mitra, S. Lumetta and M. Mitzenmacher, “X-Tolerant Signature Analysis,” IEEE Intl. Test Conf., pp. 432-441, 2004.
  151. K. Brand, S.Mitra, E. Volkerink and E.J. McCluskey, “Speed Clustering of Integrated Circuits,” IEEE Intl. Test Conf., pp. 1128-1137, 2004.
  152. M. Tahoori and S. Mitra, “Interconnect Delay Testing of Designs on Programmable Logic Devices,” IEEE Intl. Test Conf., 2004.
  153. S. Mitra and K.S. Kim, “XPAND: Test Stimulus Compression for Intel Designs,” Intel Design and Test Technology Conf., 2004.
  154. P. Johnson, D. Wu, S. Mitra and S. Venkataraman, “Elimination of System Test from Production Test Flow,” Intel Quality and Reliability Technical Symp., 2004.
  155. S. Mitra and K.S. Kim, “Xpand + X-Compact: What did we Learn?”, IEEE VLSI Test Symp., 2004 (Invited).
  156. S. Mitra, E. Volkerink, E.J. McCluskey and S. Eichenberger, “Delay Defect Screening using Process Monitor Structures,” IEEE VLSI Test Symp., pp. 43-48, 2004.
  157. E.J. McCluskey, S. Mitra, et al., “ELF-MURPHY Data on Defects and Test Sets,” IEEE VLSI Test Symp., pp. 16-22, 2004.
  158. M. Tahoori and S. Mitra, “Defect and Fault Tolerance for Reconfigurable Molecular Computing,” IEEE Field Programmable Custom Computing Machines (FCCM), pp. 176-185, 2004.
  159. S. Mitra, H. Nguyen, N. Tam and K.S. Kim, “Soft Errors in Digital Logic,” Intel Quality and Reliability Technical Symp., 2003.
  160. S. Mitra and K.S. Kim, “XMAX: X-Tolerant Architecture for Maximal Test Compression,” IEEE Intl. Conf. Computer Design, pp. 326-330, 2003. (Invited)
  161. S. Lumetta and S. Mitra, “X-Codes: Error Control with Unknowable Inputs,” IEEE Intl. Symp. Information Theory, p. 102, 2003.
  162. D. Wu, M. Lin, S. Mitra, et al., “H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing,” IEEE Intl. Test Conf., pp. 1229-1238, 2003.
  163. S. Mitra, S. Kallepalli and K.S. Kim, “Analysis of X-Compact for Intel ASIC Designs,” Intel Design and Test Technology Conf., 2003.
  164. S. Mitra, K.S. Kim and G.C. Parrish, “Design for Guaranteed Test Stimulus Compression,” Intel Design and Test Technology Conf., 2003.
  165. E. Volkerink and S. Mitra, “Efficient Seed Utilization for Reseeding based Compression,” IEEE VLSI Test Symp., pp. 232-237, 2003.
  166. M. Tahoori and S. Mitra, “Automatic Configuration Generation for FPGA Interconnect Testing,” IEEE VLSI Test Symp., pp. 134-139, 2003.
  167. A. Al Yamani, S. Mitra and E.J. McCluskey, “BIST Reseeding with Very Few Seeds,” IEEE VLSI Test Symp. , pp. 69-74, 2003.
  168. S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” IEEE Intl. Test Conf., pp. 311-320, 2002.
  169. E. Volkerink, S. Mitra and A. Khoche, “Packet Based Test Vector Compression Techniques,” IEEE Intl. Test Conf., pp. 154-163, 2002.
  170. S. Mitra and K.S. Kim, “Efficient Response Compaction,” Intel Design and Test Technology Conf., July 2002.
  171. A. Khoche, S. Mitra and E. Volkerink, “Test Vector Compression using EDA-ATE Synergies,” IEEE VLSI Test Symp., pp. 97-102, 2002.
  172. S. Mitra and E.J. McCluskey, “Dependable Reconfigurable Computing: Design Diversity and Self-Repair,” NASA/DoD Intl. Conf. Evolvable Hardware, 2002. (Invited)
  173. M. Tahoori, S. Mitra and E.J. McCluskey, “Fault Grading FPGA Interconnect Test Configurations,” IEEE Intl. Test Conf., pp. 608-617, 2002.
  174. S. Mitra, E.J. McCluskey and S. Makar, “Design for Testability and Testing of IEEE 1149.1 TAP Controller,” IEEE VLSI Test Symp., pp. 247-252, 2002.
  175. A. Al-Yamani, S. Mitra, E.J. McCluskey, “Testing Digital Circuits with Constraints,” IEEE Intl. Symp. Defect Fault Tolerance, 2002.
  176. S. Mitra, N. Saxena and E.J. McCluskey, “Techniques for Estimation of Design Diversity for Combinational Logic Circuits,” IEEE Intl. Conf. Dependable Systems and Networks, pp. 25-34, 2001.
  177. S. Mitra and E.J. McCluskey, “Design Diversity for Concurrent Error Detection in Sequential Logic Circuits,” IEEE VLSI Test Symp., pp. 178-183, 2001.
  178. S. Mitra and E.J. McCluskey, “Design of Redundant Systems Protected Against Common-Mode Failures,” IEEE VLSI Test Symp., pp. 190-195, 2001.
  179. W-J. Huang, S. Mitra and E. J. McCluskey, “Fast Run-Time Fault Location for Dependable FPGA Applications,” IEEE Intl. Symp. Defect and Fault Tolerance, pp. 206-214, 2001.
  180. C.W. Tseng, S. Mitra, E.J. McCluskey and S. Davidson, “An Evaluation of Pseudo-Random Testing for Detecting Real Defects,” IEEE VLSI Test Symp., pp. 404-409, 2001.
  181. S. Mitra and E.J. McCluskey, “Which Concurrent Error Detection Scheme to Choose?,” IEEE Intl. Test Conf., pp. 985-994, 2000.
  182. S. Mitra and E.J. McCluskey, “Combinational Logic Synthesis for Diversity in Duplex Systems,” IEEE Intl. Test Conf., pp. 179-188, 2000.
  183. S. Mitra and E.J. McCluskey, “WORD VOTER: A New Voter Design for Triple Modular Redundant Systems,” IEEE VLSI Test Symp., pp. 465-470, 2000.
  184. S. Mitra, N. Saxena and E.J. McCluskey, “Fault Escapes in Duplex Systems,” IEEE VLSI Test Symp., pp. 453-458, 2000.
  185. P. Shirvani, S. Mitra, J. Ebergen, and M. Rocken, “DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits,” Intl. Symp. Asynchronous Circuits and Systems, pp. 73-82, 2000.
  186. S. Mitra, N.R. Saxena, and E.J. McCluskey, “A Design Diversity Metric and Reliability Analysis For Redundant Systems,” IEEE Intl. Test Conf., pp. 662-671, 1999.
  187. P. Shirvani, S. Mitra, et al., “Fault-Tolerance Projects at Stanford CRC,” Military Applications Programmable Devices Conf., P23, 1999.
  188. S. Mitra, L.J. Avra and E.J. McCluskey, “An Output Encoding Problem and a Solution Technique,” IEEE/ACM Intl. Conf. Computer-Aided Design, pp. 304-307, 1997.
  189. S. Mitra, L.J. Avra and E.J. McCluskey, “Scan Synthesis for One-hot Signals,” IEEE Intl. Test Conf., pp. 714-722, 1997.

 

Book Chapters:

  1. D. Rich, A. Bartolo, C. Gilardi, B. Le, H. Li, R. Park, R. Radway, M. Aly, H.-S.P. Wong and S. Mitra, “Heterogeneous 3D NanoSystems: The N3XT Approach,” in Frontiers Collection: Chips 2030, Springer, 2020 (Invited).
  2. A. Rahimi, T.F. Wu, H. Li, J. Rabaey, H.-S.P. Wong, M. Shulaker and S. Mitra, “Hyperdimensional Computing: In-memory Computing using Monolithic 3D Integration of RRAM and CNFET,” in Devices for Brain-Inspired Computing: From Materials, Devices, and Circuits to Applications – Computational Memory, Deep Learning, and Spiking Neural Networks, Elsevier, 2020 (Invited).
  3. E. Cheng and S. Mitra, “Cross-Layer Resilience,” in Cross-Layer Reliability of Computing Systems, IET, 2020 (Invited).
  4. D. Mueller-Gritschneder, E. Cheng, U. Sharif, V. Kleeberger, P. Bose, S. Mitra, U. Schlichtmann, “Cross-Layer Resilience,” in Dependable Embedded Systems, Springer, 2020 (Invited).
  5. E. Cheng and S. Mitra, “Resilience in Next-Generation Embedded Systems,” Rugged Embedded Systems, Elsevier, 2016 (Invited).
  6. M. Shulaker, H. Wei, H.-S.P. Wong and S. Mitra, “Carbon Nanotubes for Monolithic 3D ICs,” in Carbon Nanotube Interconnects: Process, Design and Application, Springer, 2016 (Invited).
  7. N. Patil, A. Lin, J. Zhang, H. Wei, H.-S.P. Wong and S. Mitra, “Imperfection-Immune Carbon Nanotube VLSI Circuits,” in Nanoelectronic Circuit Design, Springer, 2010 (Invited).
  8. S. Mitra, M. Zhang, N. Seifert, T.M. Mak and K.S. Kim, “Soft Error Resilient System Design through Error Correction,” Springer, 2007 (Invited).
  9. E.J. McCluskey and S. Mitra, “Fault-Tolerance,” in Encyclopedia on Computer Science and Engineering, CRC Press, 2004 (Invited).