The multicore movement has taken over the processor industry. Spanning embedded, desktop, and cloud applications, multicore processors offer a game-changing opportunity for improvements in power efficiency and performance. But with much legacy software in existence, manycores face the challenge of supporting existing programming models while simultaneously innovating in programming to utilize the hundreds of cores that are imminent.
Tile processors represent a new class of multicores sporting on-chip mesh interconnect and coherent distributed caches. Tile processors are extremely power-efficient and scale from a few cores to hundreds and even thousands of cores. Because Tile processors are cache-coherent, they can use the popular shared-memory model to run existing software. In addition, the latest generation of Tile processors provides several architectural innovations to support new and upcoming programming paradigms.
This talk will discuss some of the fundamental challenges facing multicore processors, how Tile processors overcome these challenges, and trace through the research work at MIT on the Raw architecture that created some of the enabling technologies.
Slides:
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About the speaker:
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Anant Agarwal is a professor of EECS at MIT and a member of the CSAIL Lab. He enjoys hacking on Websim, an online circuits laboratory (google MIT websim). He is also a founder and CTO of Tilera, which created the Tile Processor. Agarwal holds a Ph.D. (1987) in EE from Stanford, and a Bachelor's from IIT Madras (1982). He led a group that developed Sparcle (1992), an early multithreaded microprocessor, and Alewife, a scalable shared-memory multiprocessor (1993). He led the Raw project, which developed an early tiled multicore processor. Agarwal also led the VirtualWires project at MIT and founded Virtual Machine Works (1993). Agarwal won the Wilkes prize for computer architecture in 2001 and the Smullin Award for teaching at MIT in 2005. He holds a Guinness World Record for the largest beamforming acoustic microphone array (LOUD) based on the Raw processor. He is an author of the textbook “Foundations of Analog and Digital Electronic Circuits. |
Contact information:
Anant Agarwal
32-G782
CSAIL, MIT
Cambridge, MA 02139
617 253 1448
agarwal@cag.csail.mit.edu