Computer Systems Laboratory Colloquium

4:15PM, Wednesday, October 1, 1996
NEC Auditorium, Gates Computer Science Building B03

The ATLAS I Single-Chip ATM Switch:
Toward Universal Networking with Advanced Flow Control Architectures

Manolis Katevenis
FORTH and University of Crete, Greece

ATLAS I is a single-chip ATM switch with optional credit-based (backpressure) flow control. This 4-million-transistor 0.35-micron CMOS chip, which is about to be taped out for fabrication, offers 20 Gbit/s aggregate I/O throughput, 16 serial gigabaud I/O links with link bundling, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. ATLAS I is a general-purpose building block for high-speed communication in wide (WAN), local (LAN), and system (SAN) area networking, supporting a mixture of services from real-time, guaranteed quality-of-service to best-effort, bursty and flooding traffic, in a range of applications from telecom to multimedia and multiprocessor NOW.

This talk will describe the architecture of ATLAS I and how to use it in systems. We will show how its multilane backpressure can be used inside large switch boxes to offer the high performance of output queueing at the low cost of input queueing, how this internal backpressure is interfaced to the external (rate or credit based) flow control, and how the ATLAS backpressure protocol compares favorably to the wormhole protocol.

We will argue that cell-based switching, per-connection queueing, and hop-by-hop flow control are essential features for universal networking with high quality of service. Modern VLSI technology is ripe for implementing them at gigabit speeds.

About the speaker:

Manolis Katevenis is a professor of Computer Science at the University of Crete; he heads the Computer Architecture and VLSI Systems Division of the Institute of Computer Science, Foundation for Research & Technology -- Hellas (FORTH), in Heraklion, Crete, Greece. He was an Assistant Professor of Computer Science at Stanford University in 1984-85. In 1980-83, his research was on RISC architectures. Since 1984, his research focuses on architectures and hardware implementation for high-speed networking with fairness and QoS.

Manolis Katevenis is spending his Fall'97 semester of Sabbatical leave in the San Francisco Bay Area.

Instructor's Comments:

For additional information see http://www.ics.forth.gr/proj/arch-vlsi/asiccom.html .

Contact information:

Manolis Katevenis
kateveni@cs.berkeley.edu