Jul 2,1997
Grant McFarland, Stanford Unviersity
CMOS Technology Scaling and its Impact on Cache Desig

Speaker: Grant McFarland

Title: CMOS Technology Scaling and its Impact on Cache Design

Date: April 16, 1997

Abstract:

The electrical and reliability requirements of MOSFETs are discussed and modeled to predict the scaling trends of digital bulk CMOS circuits. Limits discussed include subthreshold leakage, time dependent dielectric breakdown (TDDB), hot carrier effects (HCE), and short channel effects (SCE). The prediction is made that current scaling trends will reach their limits for high performance microprocessors at drawn lengths of approximately 0.1um. These projections of CMOS technology scaling are then applied to an on-chip cache delay model which predicts that at 0.1um, a single cycle on-chip cache will be limited to 16-32KB.

Biography:

Grant McFarland is a sixth year PhD student in the Stanford Computer Architecture and Arithmetic Group headed by Dr. Michael Flynn. He has worked previously on the cache design for the PPC 615 and will begin work in August for Intel as a design engineer on the next generation x86 microprocessor.

Contact:

Grant McFarland
Stanford University Gates 332A
Phone Office : (415) 723-3654
E-mail : farland@umunhum.stanford.edu

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