Index of /class/ee311/NOTES

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[   ]ExamExampleMidterm.pdf1999-05-03 12:35 71K 
[   ]ExamExample.pdf2001-05-21 10:40 305K 
[   ]Plummer.pdf2003-04-03 16:57 722K 
[   ]Intel_30nm.pdf2003-04-03 16:58 1.7M 
[   ]Nanoscale CMOS.pdf2003-04-03 17:04 1.5M 
[   ]GateOx_Momose.pdf2003-04-04 14:30 294K 
[   ]GateOx_Yang.pdf2003-04-04 14:37 235K 
[   ]GateOx_Schuegraf.pdf2003-04-04 14:37 613K 
[   ]NitOx_Kwong.pdf2003-04-04 14:51 257K 
[   ]GateOxNO_Kwong.pdf2003-04-04 14:52 721K 
[   ]GateOx_Gupta.pdf2003-04-04 15:03 115K 
[   ]Wilk_HighK.pdf2003-04-12 09:31 1.5M 
[   ]WooTED1-02.pdf2003-04-14 18:06 225K 
[   ]WooTED2-02.pdf2003-04-14 18:06 204K 
[   ]Contacts.pdf2003-04-17 17:24 683K 
[   ]isolationSmeys.pdf2003-04-21 13:30 283K 
[   ]IBM_Silicides_Mann.pdf2003-05-13 17:38 2.0M 
[   ]Interconnect_Havemann.pdf2003-05-13 17:38 1.1M 
[   ]Kapur2.pdf2003-05-13 17:40 313K 
[   ]Kapur1.pdf2003-05-13 17:40 383K 
[   ]LokeCh1.pdf2003-05-13 17:41 2.5M 
[   ]LokeCh2.pdf2003-05-13 17:41 192K 
[   ]LokeCh3.pdf2003-05-13 17:41 58K 
[   ]PWong_BeyondMOS.pdf2003-05-29 22:59 2.1M 
[   ]Miller_ProcIEEE.pdf2003-06-02 14:18 336K 
[   ]3DProc_IEEE.pdf2003-06-02 14:23 722K 
[   ]Trends.pdf2004-03-23 14:52 1.7M 
[   ]GateDielectric.pdf2004-04-09 23:15 2.6M 
[   ]Ohmic_Contacts.pdf2004-04-13 23:09 1.6M 
[   ]InterconnectScalingThermal.pdf2004-04-23 07:25 231K 
[   ]InterconnectThermalModeling.pdf2004-04-23 07:25 120K 
[   ]PowerModeling.pdf2004-04-23 07:25 59K 
[   ]TSUPREM4.pdf2004-04-27 11:05 72K 
[   ]TSUPREM4_Slides.pdf2004-04-27 11:05 143K 
[   ]Interconnect_Al.pdf2004-04-27 15:33 2.5M 
[   ]Silicides.pdf2004-04-28 16:11 2.2M 
[   ]Isolation.pdf2004-05-17 12:06 2.0M 
[   ]Deposition_Planarization.pdf2004-05-20 14:16 1.5M 
[   ]Gate_Dielectric_Slides_Part1.pdf2005-04-04 18:18 2.4M 
[   ]Gate_Dielectric_Slides_Part2.pdf2005-04-07 15:53 4.4M 
[   ]Ohmic_Contacts_Slides.pdf2005-04-25 22:45 1.8M 
[   ]Silicides & Metal gate Slides.pdf2005-04-28 15:56 3.6M 
[   ]Robertson JAP04.pdf2005-04-28 16:13 2.0M 
[   ]King JAP2002.pdf2005-04-28 16:13 210K 
[   ]Cu_Interconnect_Slides.pdf2005-05-07 16:16 3.6M 
[   ]Strained Silicon Technology.pdf2005-05-20 10:44 2.1M 
[   ]Future Devices.pdf2005-05-26 13:17 9.9M 
[   ]Rim IEDM95.pdf2005-05-29 13:33 355K 
[   ]Rim IEEE TED2000.pdf2005-05-29 13:33 220K 
[   ]Intel Strained-Si-IEDM03.pdf2005-05-29 13:35 511K 
[   ]Intel Strain Si EDL04.pdf2005-05-29 13:35 137K 
[   ]Hutchby_ProcIEEE03.pdf2005-05-29 13:57 1.0M 
[   ]TrendsSlides.pdf2006-04-04 22:29 6.2M 
[   ]ShallowJunctions.pdf2006-04-10 16:39 1.2M 
[   ]Shallow Junctions Slides.pdf2006-04-10 16:46 4.9M 
[   ]Interconnect Al Slides.pdf2006-05-08 14:28 2.7M 
[   ]InterconnectScalingSlides.pdf2006-05-11 17:59 4.5M 
[   ]Interconnect Scaling.pdf2006-05-11 18:01 1.9M 
[   ]Interconnect Cu Slides.pdf2006-05-15 11:00 2.6M 
[   ]Interconnect_Cu.pdf2006-05-15 11:09 4.0M 
[   ]Interconnect Lowk.pdf2006-05-18 17:58 2.6M 
[   ]Interconnect_Future.pdf2006-05-23 14:02 9.2M 
[   ]Naeemi IEDM04.pdf2006-05-23 14:16 670K 
[   ]BORKAR.PDF2006-05-24 13:46 1.1M 
[   ]SCOTT CROWDER.PDF2006-05-24 13:46 2.2M 
[   ]kapur IEDM04.pdf2006-05-24 13:48 1.7M 
[   ]Future Devices 2.pdf2006-06-01 22:00 4.3M 
[   ]Future Devices 3.pdf2006-06-05 14:43 5.6M