Xilinx CoreGen Elements in ModelSim

If you have any questions, email jcoburn@stanford.edu

The Xilinx ISE toolset allows you to add logic blocks created with the Core Generator. These logic blocks can be instantiated in your design. However, they are not readily available to simulate in ModelSim. To simulate elements such as BRAMs or multipliers, follow the steps below to create a CoreGen wrapper file and compile the CoreGen libraries to run on ModelSim.

In order to simulate CoreGen elements in Modelsim, ModelSim must be made aware of the Xilinx CoreGen simulation models. Xilinx Solution Record #15338 provides instructions to do this for us. Make sure to use the ModelSim SE instructions. This needs to be done once for each ModelSim install. All you really need to do is type compxlib -s mti_se -f all -l all -o c:\modeltech_5.7a\xilinx_libs at a command prompt.

Creating a CoreGen Wrapper File

Implement a multiplier in CoreGen. For this example, I made a parallel multiplier with two 8-bit signed inputs (non-registered) and a single 16-bit registered output. I also chose minimum pipelining so the output latency is only one cycle.

Simulation Method

Line 22 loads the CoreGen library file that was created above
Line 23 compiles the three verilog source files (note that paul_bram.v was generated by coregen)
Line 24 loads the modules into the simulator
Line 25 runs the modules

The testbench file includes the line "`timescale 1ns/10ps" that ensures all the simulation delay times are correlated. We are not using that feature and its only there to keep down some warnings in Modelsim.

The source files used for this example are here.

If you have any questions, email jcoburn@stanford.edu