EE 121                                         Lecture date: September 26, 2002
Digital Design Laboratory                                            Handout #2

			     Lecture #1 Outline

Lecture Topics
 * Course introduction: staff, structure, calendar
 * Course outline: goals and topics

COURSE INTRODUCTION

Information sheet

* Instructor: John Gill, office Packard 266

* TAs: James Nielsen, Sam Mazin, Ernesto Staroswiecki
  Note: students should feel free to ask help from any available TA

* Text: Wakerly's DDPP.  Be sure to get third edition (any version).

* Lectures: 17 x 75 minutes = 21 hours (digital design principles)

* Labs: 6 x 6 hours and final project (40 hours?) (digital design practices)

* Exams and homework: 3 to 6 short homework assignments, two midterms

Laboratory format

* Each student is assigned to a lab section that meets at the same time each
  week with the same TA.  Tentatively, labs meet in weeks #3 through #7.

* There will be three CAD lab assignments (computer designed and simulated),
  and three hardware labs in which circuits are constructed and debugged.


COURSE GOALS

What you will learn in the course

* State machines: how to design, simulate, and debug a digital system
  consisting of interconnected state machines.

* Knowledge of the "second kind" (industry standards)
  + Common digital logic families
  + How to use and design standard components like decoders and counters
  + Analog-to-digital and digital-to-analog converters
  + FPGA architectures and memory devices

* How to read data sheets (very important).

* Sadly, few practical aspects of circuit construction (e.g., which end of
  soldering iron is hot) because FPGAs eliminate most wiring.

Important: the purpose of the laboratory assignments is to demonstrate
understanding of the course material and proper design techniques.

* The primary goal is NOT simply to make the design work.

* Solutions require careful, systematic thinking; usually no magic kludges.

* Warning: most final projects can be easily built using microprocessors;
  designing them using PLDs and MSI gates is of educational value.


COURSE OUTLINE

Textbook coverage: parts of Chapters 1 through 11, at least 400 pages.

Topics to be covered in lectures and laboratory assignments

* Introduction to CMOS logic circuits (DDPP Chapter 3)
  + How basic logic gates are built using p- and n-channel transistors
    (In today's technology, transistors are the objects at the bottom of
    design hierarchy.)
  + Speed, power, fanout

* Combinational logic design principles, practices, examples (DDPP Chapters 4-6)
  + Boolean functions and their representations
  + Analysis and synthesis of logic circuits that realize Boolean functions
  + Useful combinational building blocks: decoders, multiplexers, etc.
    (Many of these structures were implemented as integrated circuits in
    the 74x TTL logic families.  Now they are universally available as
    components--hard or soft macros--in gate array libraries.)
  + Three-state outputs, open collector outputs, drivers

* Sequential logic design principles, practices, examples (DDPP Chapters 7-9)
  + Elementary devices with memory: latches and flip-flops
    (We will learn how latches and flip-flops are built, but the emphasis
    will be on their proper use.)
  + State machines: description, analysis, synthesis
  + Important sequential building blocks: counters, shift registers
  + Synchronous design methodology: the "right" way to design digital systems

* Memory (DDPP Chapter 10)
  + How to use ROM (read only memory) and RAM (random access memory)

* Introduction to gate arrays, cell libraries, and logic synthesis 
  + Survey of Complex Programmable Logic Devices (CPLD)
  + Introduction to hardware description languages (EDIF, Verilog, VHDL)


DIGITAL DESIGN DESCRIPTIONS

* Boolean equations (not adequate for most designs, like sequential circuits)

* Schematics show components and interconnections (but usually not physical
  layout).   A schematic can be converted to a netlist, a textual description
  that usually omits graphical information.

* Hardware description language (VHDL, Verilog) can (in principle) give a
  complete description of the design, including timing requirements.

The "right" way to design a digital system is "hierarchical design."  This is
analogous to top-down programming.  The main circuit consists of interconnected
subcircuits, which contain subsubcircuits, and so on.  Top-down design proceeds
as follows:

* Decompose the problem into parts: choose the components and interface
  specifications (input/output signals and timing constraints)

* Design the components (perhaps in parallel)

* Assemble the components, test, debug, revise

Standard useful components are often employed (decoders, comparators, adders).
In olden times, all systems were built using standard, off-the-shelf parts.
Today, standard components are used to reduce the intellectual effort, but the
components can also be modified when necessary.

With Xilinx Foundation schematic capture software, you will pick parts and
connect (and disconnect) them to create subcircuits that will be used in larger
circuits.  (No recursion allowed.)  The components will be constructed either
from schematics, HDL, or bevavioral models (program simulating a component).


DIGITAL DESIGN EXAMPLE

Example: simple alarm system

Sensors at three doors.  When enabled, the alarm is activated when any door
opens.  Input signals: ENABLE, DOOR1, DOOR2, DOOR3 (abbreviated EN, D1, D2, D3).
Output signal: ALARM (presumably drives a loudspeaker).
Circuit descriptions:

* Boolean equation: ALARM = EN * (D1 + D2 + D3)

* HDL (ABEL): ALARM = EN & (D1 # D2 # D3);

* Schematic: 3-input OR gate can replace two 2-input OR gates.

This combinational circuit can be easily translated into a schematic; in this
case, and for many combinational circuits, the synthesis problem is trivial.

Example: more realistic alarm system

The alarm sounds when any door is open unless the alarm is disabled within 15
seconds.

* Software:
  while (!(D1 || D2 || D3)) {
    /* relax */
  }
  for (i = 0; i < 15; i++) {
    beep();   /* turn on alarm for brief time */
    sleep(1);
  }
  ALARM = EN; /* sound alarm if still enabled */

* schematic: counters, state machine, using basic memory element--flip-flop


Reading assignment for weeks #1 and #2

* Chapter 1.  You should read this chapter again later in the quarter.

* Chapter 2. 
  + 2.1 - 2.6.  This material should be familiar to most students.
  + 2.10, 2.11, 2.13.  These sections are needed later.

* Chapter 3.
  + 3.1 - 3.4.  Introduction to CMOS circuits for logic gates
  + 3.7.  Important special input and output structures (discussed later)